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fD$$AF\D$ HDH$ff u1DffT$T$& T$ T$T$T$AFAAT$DfH4$HT$T$$T$ T$ 1H([]A\A]A^A_AՉT$'>A`A@|ff.USoHHøfSfHHS1[]ff.AUATIUSHoHUIf؃fHLݺHSAT$`HH1[]A\A]fATUSH_ALSLS1LSHSHffHHH1[]A\ff.AVAAUAATIUHSHAUHDfLAUHfHEfAEu)oArHHDHfHAHDHt[]A\A]A^[1]A\A]A^ff.@AVAAUAATIUHSHAUHDfLAUHfHEfA Eu)oArHHDHfHAHDHt[]A\A]A^[1]A\A]A^ff.@AVAAUATIUHSHASHDfLSHfHEfEtsAIHDHƉfHAr$HHӅt[]A\A]A^[1]A\A]A^AWAVAAUAATIUHSHIHI@AVHDfLAVHfHEeE~ AFfD$EtzHDHfT$AfHAHUDHu\HDHuIAsH1[]A\A]A^A_H[]A\A]A^A_ff.AWAVAAUATAUHSHHHEH@AT$HƉfHAT$HfHEfEtEu HKHՅHHAׅupHDHƉfAUDfHAs[1]A\A]A^A_[]A\A]A^A_ff.AVAUATIUSHDsDIffffA4$fDfHL[1]A\A]A^IHHHHIHHHHHHHHHHHHHHHt$HHHщHH@ @ @ @HHHHHv;ۀLd$( 1LH@$tHu^HHHHt$LHHHHt$HHHHt$HHHHHHHH/H11HHeH%(H$1ILt(wЃ=ttHtH91LLlj$DŽ$ HD$HDŽ$H$eH+%(tHHHH1HHHH1HHD$L$HT$ L$t$ PD$PDL$"DD$ XZL$Aȉ‰HL$D L$1HHH|$t$ sffSfwCfCHCHfC1HHHHE1EHDKHHHD$HƉHHD$T$D H5HbHT$T$H6H#HD$HHD$HHHL$L$HHHHHHHHAt$HE5f{ufCsH{tmDHt$H5HHH5@DH5D$H[H]HHHHHHHHHHHHHHs HHH1HHHHHH1{11CHH̋SsHsHHs"HHHHhHHIHH)HH HHHHHH;1HHHHHHHHHHHMAHщHH;MAHщHH;HH ڃD$Du At$HDAHDSDSDD$XH[]A\A]A^A_HHHHHHHA~t+AvHHHH1҉HHA׾HHHHHHHT$T$HHHT$T$HIHHADHHIHHADHHIHHDHHIHHAADHHIHHADHLHA4$HHA$USt HH1f-HHffHHHfǃH HuHtHtHHtHtHHtHtHHtHtHWHyH25=ffy"HH[]mwave_uart_iomwave_uart_irqmwave_3780i_iomwave_3780i_irqmwave_debug00N000Pp mwavedd::mwave_write entry file %p, buf %p, count %zx ppos %p mwavedd::mwave_read entry file %p, buf %p, count %zx ppos %p mwavedd::mwave_ioctl, entry file %p cmd %x arg %x mwavedd::mwave_ioctl, IOCTL_MW_RESET calling tp3780I_ResetDSP mwavedd::mwave_ioctl, IOCTL_MW_RESET retval %x from tp3780I_ResetDSP mwavedd::mwave_ioctl, IOCTL_MW_RUN calling tp3780I_StartDSP mwavedd::mwave_ioctl, IOCTL_MW_RUN retval %x from tp3780I_StartDSP mwavedd::mwave_ioctl, IOCTL_MW_DSP_ABILITIES calling tp3780I_QueryAbilities mwavedd::mwave_ioctl, IOCTL_MW_DSP_ABILITIES retval %x from tp3780I_QueryAbilities mwavedd::mwave_ioctl, IOCTL_MW_DSP_ABILITIES exit retval %x mwavedd::mwave_ioctl IOCTL_MW_READ_DATA, size %lx, ioarg %lx pusBuffer %p mwavedd::mwave_ioctl IOCTL_MW_READ_INST, size %lx, ioarg %lx pusBuffer %p mwavedd::mwave_ioctl IOCTL_MW_WRITE_DATA, size %lx, ioarg %lx pusBuffer %p mwavedd::mwave_ioctl IOCTL_MW_WRITE_INST, size %lx, ioarg %lx pusBuffer %p 3mwave: mwavedd::mwave_ioctl: IOCTL_MW_REGISTER_IPC: Error: Invalid ipcnum %x mwavedd::mwave_ioctl IOCTL_MW_REGISTER_IPC ipcnum %x entry usIntCount %x mwavedd::mwave_ioctl IOCTL_MW_REGISTER_IPC ipcnum %x exit 3mwave: mwavedd::mwave_ioctl: IOCTL_MW_GET_IPC: Error: Invalid ipcnum %x mwavedd::mwave_ioctl IOCTL_MW_GET_IPC ipcnum %x, usIntCount %x mwavedd::mwave_ioctl, thread for ipc %x going to sleep mwavedd::mwave_ioctl IOCTL_MW_GET_IPC ipcnum %x handling first int mwavedd::mwave_ioctl IOCTL_MW_GET_IPC ipcnum %x woke up and returning to application mwavedd::mwave_ioctl IOCTL_MW_GET_IPC, returning thread for ipc %x processing mwavedd::mwave_ioctl IOCTL_MW_UNREGISTER_IPC ipcnum %x 3mwave: mwavedd::mwave_ioctl: IOCTL_MW_UNREGISTER_IPC: Error: Invalid ipcnum %x mwavedd::mwave_ioctl, exit retval %x 3mwave: mwavedd::register_serial_portandirq: Error: Illegal port %x 3mwave: mwavedd::register_serial_portandirq: Error: Illegal irq %x &pDrvData->IPCs[i].ipc_wait_queuemwavedd::mwave_init, return from tp3780I_InitializeBoardData retval %x 3mwave: mwavedd::mwave_init: Error: Failed to initialize board data mwavedd::mwave_init, return from tp3780I_CalcResources retval %x 3mwave: mwavedd:mwave_init: Error: Failed to calculate resources mwavedd::mwave_init, return from tp3780I_ClaimResources retval %x 3mwave: mwavedd:mwave_init: Error: Failed to claim resources mwavedd::mwave_init, return from tp3780I_EnableDSP retval %x 3mwave: mwavedd:mwave_init: Error: Failed to enable DSP 3mwave: mwavedd:mwave_init: Error: Failed to register misc device 3mwave: mwavedd:mwave_init: Error: Failed to register serial driver 3mwave: mwavedd::mwave_init: Error: Failed to initialize mwavedd::mwave_close, entry inode %p file %p mwavedd::mwave_close, exit retval %x mwavedd::mwave_open, entry inode %p file %p mwavedd::mwave_open, exit return retval %x inBX %x inCX %x inDI %x inSI %x myoutAX %x myoutBX %x myoutCX %x myoutDX %x myoutDI %x myoutSI %x usSmapiOK %x smapi::smapi_request exit retval %x smapi::smapi_query_DSP_cfg entry 3mwave: smapi::smapi_query_DSP_cfg: Error: Could not get DSP Settings. Aborting. smapi::smapi_query_DSP_cfg, smapi_request OK smapi::smapi_query_DSP_cfg get DSP Settings bDSPPresent %x bDSPEnabled %x usDspIRQ %x usDspDMA %x usDspBaseIO %x 3mwave: smapi::smapi_query_DSP_cfg: Worry: DSP base I/O address is 0 3mwave: smapi::smapi_query_DSP_cfg: Worry: DSP IRQ line is 0 smapi::smapi_query_DSP_cfg: Error: Could not get DSP modem settings. Aborting. smapi::smapi_query_DSP_cfg get DSP modem settings bModemEnabled %x usUartIRQ %x usUartBaseIO %x 3mwave: smapi::smapi_query_DSP_cfg: Worry: UART base I/O address is 0 3mwave: smapi::smapi_query_DSP_cfg: Worry: UART IRQ line is 0 smapi::smapi_query_DSP_cfg exit bRC %x smapi::smapi_set_DSP_cfg entry mwave_3780i_irq %x mwave_3780i_io %x mwave_uart_irq %x mwave_uart_io %x 3mwave: smapi::smapi_set_DSP_cfg: Error: Invalid mwave_3780i_io address %x. Aborting. 3mwave: smapi::smapi_set_DSP_cfg: Error: Invalid mwave_3780i_irq %x. Aborting. 3mwave: smapi::smapi_set_DSP_cfg: Error: Invalid mwave_uart_io address %x. Aborting. 3mwave: smapi::smapi_set_DSP_cfg: Error: Invalid mwave_uart_irq %x. Aborting. 3mwave: smapi::smapi_set_DSP_cfg: Serial port A irq %x conflicts with mwave_uart_irq %x 3mwave: smapi::smapi_set_DSP_cfg: Serial port A base I/O address %x conflicts with mwave uart I/O %x 3mwave: smapi::smapi_set_DSP_cfg: Serial port B irq %x conflicts with mwave_uart_irq %x 3mwave: smapi::smapi_set_DSP_cfg: Serial port B base I/O address %x conflicts with mwave uart I/O %x 3mwave: smapi::smapi_set_DSP_cfg: IR port irq %x conflicts with mwave_uart_irq %x 3mwave: smapi::smapi_set_DSP_cfg: IR port base I/O address %x conflicts with mwave uart I/O %x smapi::smapi_set_DSP_cfg exit 3mwave: smapi::smapi_set_DSP_cfg exit on smapi_request error bRC %x smapi::smapi_set_DSP_power_state entry bOn %x smapi::smapi_set_DSP_power_state exit bRC %x smapi::smapi_init usSmapiID %x smapi::smapi_init, ERROR unable to read from SMAPI port smapi::smapi_init, exit true g_usSmapiPort %x smapi::smapi_init, ERROR invalid usSmapiID tp3780i::UartInterrupt entry irq %x dev_id %p tp3780i::DspInterrupt entry irq %x dev_id %p tp3780i::DspInterrupt, return from dsp3780i_GetIPCSource, usIPCSource %x tp3780i::DspInterrupt usPCNum %x usIPCSource %x tp3780i::DspInterrupt usIntCount %x tp3780i::DspInterrupt, waking up usPCNum %x tp3780i::DspInterrupt, no one waiting for IPC %x tp3780i::DspInterrupt, return false from dsp3780i_GetIPCSource tp3780i::tp3780I_InitializeBoardData entry pBDData %p 3mwave: tp3780i::tp3780I_InitializeBoardData: Error: SMAPI is not available on this machine tp3780i::tp3780I_InitializeBoardData exit retval %x tp3780i::tp3780I_Cleanup entry and exit pBDData %p tp3780i::tp3780I_CalcResources entry pBDData %p 3mwave: tp3780i::tp3780I_CalcResources: Error: Could not query DSP config. Aborting. 3mwave: tp3780i::tp3780I_CalcResources: Error: Illegal resource setting. Aborting. tp3780i::tp3780I_CalcResources exit tp3780i::tp3780I_ClaimResources entry pBDData %p 3mwave: tp3780i::tp3780I_ClaimResources: Error: Could not claim I/O region starting at %x tp3780i::tp3780I_ClaimResources exit retval %x tp3780i::tp3780I_ReleaseResources entry pBDData %p tp3780i::tp3780I_ReleaseResources exit retval %x tp3780i::tp3780I_EnableDSP entry pBDData %p 3mwave: tp3780i::tp3780I_EnableDSP: Error: DSP already enabled! tp3780i::tp3780I_EnableDSP: Cleaning up 3mwave: tp3780::tp3780I_EnableDSP: Error: pSettings->bDSPEnabled not set 3mwave: tp3780i::tp3780I_EnableDSP: Error: invalid irq %x 3mwave: tp3780i::tp3780I_EnableDSP: Error: Invalid DSP base I/O address %x 3mwave: tp3780i::tp3780I_EnableDSP: Error: Invalid UART IRQ %x tp3780i::tp3780I_EnableDSP: Error: Invalid UART base I/O address %x 3mwave: tp3780i::tp3780I_EnableDSP: Error: Could not get UART IRQ %x tp3780i::tp3780I_EnableDSP: Error: Could not get 3780i IRQ %x tp3780i::tp3780I_EnableDSP, got interrupt %x bShareDspIrq %x 3mwave: tp3780i::tp3780I_EnableDSP: Error: smapi_set_DSP_power_state(true) failed tp3780i::tp3780I_EnableDSP: Error: dsp7880I_EnableDSP() failed tp3780i::tp3780I_EnableDSP exit tp3780i::tp3780I_DisableDSP entry pBDData %p tp3780i::tp3780I_DisableDSP exit retval %x tp3780i::tp3780I_ResetDSP entry pBDData %p tp3780i::tp3780I_ResetDSP exit retval %x tp3780i::tp3780I_StartDSP entry pBDData %p tp3780i::tp3780I_StartDSP exit retval %x tp3780i::tp3780I_QueryAbilities entry pBDData %p tp3780i::tp3780I_QueryAbilities exit retval=SUCCESSFUL tp3780i::tp3780I_ReadWriteDspDStore entry pBDData %p, uOpcode %x, pvBuffer %p, uCount %x, ulDSPAddr %lx tp3780i::tp3780I_ReadWriteDspDStore exit retval %x tp3780i::tp3780I_ReadWriteDspIStore entry pBDData %p, uOpcode %x, pvBuffer %p, uCount %x, ulDSPAddr %lx tp3780i::tp3780I_ReadWriteDspIStore exit retval %x 3780i::dsp3780i_WriteGenCfg entry usDspBaseIO %x uIndex %x ucValue %x 3780i::dsp3780i_WriteGenCfg rSlaveControl %x 3780i::dsp3780i_WriteGenCfg entry rSlaveControl+ConfigMode %x 3780i::dsp3780i_WriteGenCfg exit 3780i::dsp3780I_ReadMsaCfg entry usDspBaseIO %x ulMsaAddr %lx 3780i::dsp3780I_ReadMsaCfg exit val %x 3780i::dsp3780i_WriteMsaCfg entry usDspBaseIO %x ulMsaAddr %lx usValue %x 3780i::dsp3780I_EnableDSP entry pSettings->bDSPEnabled %x 33780i::dsp3780I_EnableDSP: Error: DSP not enabled. Aborting. 3780i::dsp3780i_EnableDSP entry pSettings->bModemEnabled %x 3780i::dsp3780i_EnableDSP usDspBaseIO %x index %x taddr %x 3780i::dsp3780i_EnableDSP rSlaveContrl %x 3780i::dsp3780i_EnableDSP rSlaveControl 2 %x 3780i::dsp3780i_EnableDSP rSlaveControl 3 %x 3780i::dsp3780i_EnableDSP DSP_HBridgeControl %x rHBridgeControl %x 3780i::dsp3780I_EnableDSP exiting bRC=true, ChipID %x 3780i::dsp3780i_DisableDSP entry 3780i::dsp3780i_DisableDSP exit 3780i::dsp3780i_Reset rHBridgeControl %x 3780i::dsp3780i_Reset rBootDomain %x 3780i::dsp3780i_Reset exit bRC=0 3780i::dsp3780i_Run rHBridgeControl %x 3780i::dsp3780i_Run exit bRC=true 3780i::dsp3780I_ReadDStore entry usDspBaseIO %x, pusBuffer %p, uCount %x, ulDSPAddr %lx 3780I::dsp3780I_ReadDStore uCount %x val %x 3780I::dsp3780I_ReadDStore exit bRC=true 3780i::dsp3780I_ReadAndDStore entry usDspBaseIO %x, pusBuffer %p, uCount %x, ulDSPAddr %lx 3780I::dsp3780I_ReadAndCleanDStore uCount %x val %x 3780I::dsp3780I_ReadAndClearDStore exit bRC=true 3780i::dsp3780D_WriteDStore entry usDspBaseIO %x, pusBuffer %p, uCount %x, ulDSPAddr %lx 3780I::dsp3780I_WriteDStore uCount %x val %x 3780I::dsp3780D_WriteDStore exit bRC=true 3780i::dsp3780I_ReadIStore entry usDspBaseIO %x, pusBuffer %p, uCount %x, ulDSPAddr %lx 3780I::dsp3780I_ReadIStore uCount %x val_lo %x val_hi %x 3780I::dsp3780I_ReadIStore exit bRC=true 3780i::dsp3780I_WriteIStore entry usDspBaseIO %x, pusBuffer %p, uCount %x, ulDSPAddr %lx 3780I::dsp3780I_WriteIStore uCount %x val_lo %x val_hi %x 3780I::dsp3780I_WriteIStore exit bRC=true 3780i::dsp3780I_GetIPCSource entry usDspBaseIO %x pusIPCSource %p 3780i::dsp3780I_GetIPCSource, usIPCSource %x ~ %x 3780i::dsp3780I_GetIPCSource exit usIPCSource %x mwavedd::mwave_exit entry mwavedd::mwave_exit exit mwavedd::mwave_init entry mwavesmapi::smapi_init entry tp3780i::DspInterrupt exit tp3780i::EnableSRAM, entry tp3780i::EnableSRAM exit mwave_3780imwave_uart3780i::dsp3780i_Reset entry 3780i::dsp3780i_Run entry parmtype=mwave_uart_io:intparmtype=mwave_uart_irq:intparmtype=mwave_3780i_io:intparmtype=mwave_3780i_irq:intparmtype=mwave_debug:intlicense=GPLauthor=Mike Sullivan and Paul Schroederdescription=3780i Advanced Communications Processor (Mwave) driverdepends=retpoline=Yintree=Yname=mwavevermagic=6.1.0-41-amd64 SMP preempt mod_unload modversions  ((  (08`80( ` (08PX`hpPX`hpP80( P (08`hpx`hpx`hpx`hpx`hpx`hpx`hpx`hpx`hpx`hpx`80( `08@HP00 `hph`P`0  (8( 8HH (080( 8 (080( 88H8 (08@80(   (08`80( ` (0(  (  (0( 0(  (0( 0(  (0( 0(  (08@80( @80(  (080( 80(  (0( @80(  `0(0@80;JQfree_irq}Qmisc_deregisterœ_copy_from_user__get_user_2HZ__put_user_28"Jadd_wait_queueserial8250_unregister_portDC__wake_up 4_raw_spin_lock_irqsave5__release_regionm__fentry__~_printkQscheduleV __stack_chk_fail@prtc_lockՒrequest_threaded_irqKMmutex_lockdrtc_cmos_read탦current_taskp\_raw_spin_unlock_irqrestorerkdefault_llseeklioport_resourcemisc_register9[__x86_return_thunkتdefault_wake_functionk_copy_to_userT__init_waitqueue_head82mutex_unlock__const_udelayQs__SCT__cond_resched7remove_wait_queue(Vserial8250_register_8250_port<param_ops_int__request_region module_layoutmwaveGCC: (Debian 12.2.0-14+deb12u1) 12.2.0GCC: (Debian 12.2.0-14+deb12u1) 12.2.0GCC: (Debian 12.2.0-14+deb12u1) 12.2.0GCC: (Debian 12.2.0-14+deb12u1) 12.2.0GCC: (Debian 12.2.0-14+deb12u1) 12.2.0W (DD D@D`DDDDDEEE'E4E AE0QEdEkErEzEEEEEEE E E E E EEEEEF FFF&F/FEE E E E E EE8FTF^FhFsF~FF F FFF%pFD D@F`FGD GEG&G8G EG@SG`XGdGpG~GGGG G@G`GGG HH$H4H ?H@EHHKHPQHXWH`]HhcHpiHH H<@HHHH@HHH|DH I@I`!I2I =IHIKSIK[IG@jItI III@IKIKDKIKIIKII JJ1J DJLJTJk]JdJnJ J  DJJJ  DJJ J J J  K &K =K  DJSK cK K K K KKK@KkKK pK  iiaiK L L  220'L-L3L ˆ?L KL - ƈ- Ȉ- ʈ- ̈VL p aLKeL ψL p LL ҈ LLLLL;<L;<L;<L;<L;<L;<L ԈLM MM Mֈ6MCMNMXMgM vM؈MMMMMMڈMMM܈MMMMMMވM܈MNNN"N6NMENYNMeNvN܈NNNNNM NNMN NNOOOM!O.O3O8O M BOQO[OeOrO|OOMO DO;<O  DTJk]JdJO O O P +P  L?P LP [P  LoP;<wP;<P  DPPP  DPPP  DPP  # bDSPPresentbDSPEnabledbModemEnabledbMIDIEnabledbSblstEnabledusDspIRQusDspDMAusDspBaseIOusUartIRQusUartBaseIOusMidiIRQusMidiBaseIOusSndblstIRQusSndblstDMAusSndblstBaseIOSMAPI_DSP_SETTINGSLatch8Latch9Latch10Latch11Latch12Latch13Latch14Latch15Mask8Mask9Mask10Mask11Mask12Mask13Mask14Mask15DSP_GPIO_OUTPUT_DATA_15_8Enable8Enable9Enable10Enable11Enable12Enable13Enable14Enable15DSP_GPIO_DRIVER_ENABLE_15_8GpioMode8GpioMode9GpioMode10GpioMode11GpioMode12GpioMode13GpioMode14GpioMode15DSP_GPIO_MODE_15_8_DSP_3780I_CONFIG_SETTINGSusBaseConfigIObInterruptClaimedusDspIrqusDspDmausUartIrqbDspIrqActiveLowbUartIrqActiveLowbDspIrqPulsebUartIrqPulseuIpsuDStoreSizeuIStoreSizeuDmaBandwidthusNumTransfersusReRequestbEnableMEMCS16usIsaMemCmdWidthbGateIOCHRDYbEnablePwrMgmtusHBusTimerLoadValuebDisableLBusTimeoutusN_DivisorusM_MultiplierbPllBypassusChipletEnablebUartSaveducIERucFCRucLCRucMCRucSCRucDLLucDLMDSP_3780I_CONFIG_SETTINGS_MW_ABILITIESinstr_per_secinst_sizebus_dma_bwuart_enablecomponent_listmwave_os_namebios_task_nameMW_ABILITIESbShareDspIrqbShareUartIrqrDspSettingsTHINKPAD_BD_DATA_MWAVE_IPCusIntCountbIsEnabledbIsHereipc_wait_queueMWAVE_IPC_MWAVE_DEVICE_DATArBDDataulIPCSource_ISRulIPCSource_DPCbBDInitializedbResourcesClaimedbDSPResetIPCsbMwaveDevRegisteredsLinenr_registered_attrsdevice_registeredMWAVE_DEVICE_DATApMWAVE_DEVICE_DATApBDDatauOpcodepvBufferuCountulDSPAddrtp3780I_ReadWriteDspIStoretp3780I_ReadWriteDspDStorepAbilitiestp3780I_QueryAbilitiestp3780I_StartDSPtp3780I_ResetDSPtp3780I_DisableDSPtp3780I_EnableDSPtp3780I_ReleaseResourcestp3780I_ClaimResourcestp3780I_CalcResourcestp3780I_Cleanuptp3780I_InitializeBoardDataDspInterruptUartInterruptEnableSRAM_MW_READWRITEusDspAddressulDataLengthpBufMW_READWRITEmwave_initmwave_exitregister_serial_portandirqmwave_writemwave_readiocmdioargmwave_ioctlmwave_closemwave_opensmapi_initbOnsmapi_set_DSP_power_statesmapi_set_DSP_cfgpSettingssmapi_query_DSP_cfginBXinCXinDIinSIoutAXoutBXoutCXoutDXoutDIoutSIsmapi_requestClockControlSoftResetConfigModeReservedDSP_ISA_SLAVE_CONTROLEnableDspIntMemAutoIncIoAutoIncDiagnosticModeIsaPacingTimerDSP_HBRIDGE_CONTROLIrqActiveLowIrqPulseIrqBaseIODSP_UART_CFG_1EnableDSP_UART_CFG_2AccessModeDSP_HBRIDGE_CFG_1DSP_HBRIDGE_CFG_2DmaNumTransfersReRequestMEMCS16DSP_BUSMASTER_CFG_1IsaMemCmdWidthDSP_BUSMASTER_CFG_2GateIOCHRDYDSP_ISA_PROT_CFGDSP_POWER_MGMT_CFGLoadValueDSP_HBUS_TIMER_CFGNMIHaltResetCoreDSP_BOOT_DOMAINDisableTimeoutDSP_LBUS_TIMEOUT_DISABLEMemorySerialPort1SerialPort2SerialPort3GpioSoundBlasterUartMidiIsaMasterDSP_CHIP_RESETN_DivisorReserved1M_MultiplierReserved2DSP_CLOCK_CONTROL_1PllBypassDSP_CLOCK_CONTROL_2pusIPCSourcedsp3780I_GetIPCSourcedsp3780I_WriteIStoredsp3780I_ReadIStoredsp3780I_WriteDStoredsp3780I_ReadAndClearDStoredsp3780I_ReadDStoredsp3780I_Rundsp3780I_Resetdsp3780I_DisableDSPpIrqMappDmaMapdsp3780I_EnableDSPuIndexucValuedsp3780I_WriteGenCfgulMsaAddrusValuedsp3780I_WriteMsaCfgdsp3780I_ReadMsaCfg  # %  > T h)<$ @P:` Wi7B#KWF2hsx2 ( 4V((m (7P( 8Sx( P3pR(f ` ~ (C#|  p&7 E;/\ pkj.e-o 1 8i +x IF Ab ' )  0 ' ' ) .'W ;G ;gg| #| +  "T>)VEBEcD}$ImHJ@&" !N(5Ba[do@~# `X  ! 17 C  jV ^ g x p'#  ` Z#  # ^#    "& 5 E S f |   A `h @!  #  0  " #> R ] o r $ 0 $   %2 0U + < p K __UNIQUE_ID_depends195____versions__UNIQUE_ID_retpoline194__UNIQUE_ID_intree193__UNIQUE_ID_name192__UNIQUE_ID_vermagic191_note_10_note_9mwave_writemwave_write.coldmwave_readmwave_read.coldmwave_exitmwave_misc_devmwave_exit.coldmwave_ioctlmwave_mutexmwave_ioctl.coldregister_serial_portandirqmwave_init__key.14mwave_closemwave_close.coldmwave_openmwave_open.cold__UNIQUE_ID___addressable_init_module289__UNIQUE_ID___addressable_cleanup_module288mwave_fops__UNIQUE_ID_mwave_uart_iotype281__param_mwave_uart_io__param_str_mwave_uart_io__UNIQUE_ID_mwave_uart_irqtype280__param_mwave_uart_irq__param_str_mwave_uart_irq__UNIQUE_ID_mwave_3780i_iotype279__param_mwave_3780i_io__param_str_mwave_3780i_io__UNIQUE_ID_mwave_3780i_irqtype278__param_mwave_3780i_irq__param_str_mwave_3780i_irq__UNIQUE_ID_mwave_debugtype277__param_mwave_debug__param_str_mwave_debug__UNIQUE_ID_license276__UNIQUE_ID_author275__UNIQUE_ID_description274.LC21.LC36smapi_requestg_usSmapiPortsmapi_request.coldausDspBases.5ausUartBases.4smapi_query_DSP_cfg.coldausDspBases.3smapi_set_DSP_cfg.coldausUartBases.1smapi_set_DSP_power_state.coldsmapi_init.coldUartInterruptUartInterrupt.coldDspInterruptDspInterrupt.coldEnableSRAMEnableSRAM.coldtp3780I_InitializeBoardData.coldtp3780I_Cleanup.coldtp3780I_CalcResources.coldtp3780I_ClaimResources.coldtp3780I_ReleaseResources.colds_ausThinkpadIrqToFields_ausThinkpadDmaToFieldtp3780I_EnableDSP.coldtp3780I_DisableDSP.coldtp3780I_ResetDSP.coldtp3780I_StartDSP.coldtp3780I_QueryAbilities.coldtp3780I_ReadWriteDspDStore.coldtp3780I_ReadWriteDspIStore.colddsp3780I_WriteGenCfgdsp3780I_WriteGenCfg.colddsp_lockdsp3780I_ReadMsaCfg.colddsp3780I_WriteMsaCfg.colddsp3780I_EnableDSP.colddsp3780I_DisableDSP.colddsp3780I_Reset.colddsp3780I_Run.colddsp3780I_ReadDStore.colddsp3780I_ReadAndClearDStore.colddsp3780I_WriteDStore.colddsp3780I_ReadIStore.colddsp3780I_WriteIStore.colddsp3780I_GetIPCSource.coldfree_irqdsp3780I_WriteIStoremisc_deregister_copy_from_user__this_moduletp3780I_ResetDSP__get_user_2__put_user_2tp3780I_ReleaseResourcesdsp3780I_ReadMsaCfgcleanup_modulemwave_s_mddadd_wait_queueserial8250_unregister_porttp3780I_ReadWriteDspDStoredsp3780I_WriteMsaCfg__wake_up_raw_spin_lock_irqsave__release_region__fentry__tp3780I_CalcResourcesinit_moduletp3780I_DisableDSP_printkschedule__stack_chk_faildsp3780I_GetIPCSourcertc_locksmapi_query_DSP_cfgtp3780I_Cleanuprequest_threaded_irqmutex_lockrtc_cmos_readcurrent_task_raw_spin_unlock_irqrestoredsp3780I_ReadDStoredefault_llseekioport_resourcemisc_register__x86_return_thunkdefault_wake_function_copy_to_user__init_waitqueue_headtp3780I_StartDSPtp3780I_InitializeBoardDatadsp3780I_Runmutex_unlock__const_udelaysmapi_set_DSP_power_statesmapi_set_DSP_cfgdsp3780I_ReadAndClearDStore__SCT__cond_reschedsmapi_initremove_wait_queuedsp3780I_DisableDSPdsp3780I_EnableDSPtp3780I_QueryAbilitiesdsp3780I_WriteDStoreserial8250_register_8250_portparam_ops_intdsp3780I_ReadIStoretp3780I_ClaimResourcestp3780I_EnableDSP__request_regiondsp3780I_Resettp3780I_ReadWriteDspIStorez!z'.:AzGN6Ur_ternrwrrG ir r}r ror rz#j} ` r  ~ r r s  ELk\ rbm v}X `m `  r `#)0Z `_f rkr `y:S ` r r r rw `$*=!PW^ `gn7u `| r2j ` ru `Pjdkr `w r ` ` rl `j+29 `>S rXu_ `flj ` ru `&2P\RmzBztzx$ + P U a z      Z h p m ~x    F  ~ 5  ") 5 @ ] pp u z  z      ~ C$ - > D x   7   M* ]V r x   C    } 17OFpv}71zPWyfz x &- 2x?NS] gls|zzr' rL wz p%v6vGvMT [azkr- T A ze z<C KU e q   t 1z;B P \ aj ry z  y gz% ! .m <P JP U \P d kP y0 0       [c ng       J 9  !z+2 @IWcj r}gz  z  1z7H% B !zDKf qxS z  )0 ASphz zx  x3 :@G Pazsz  x z 1O8 =xSZ;i} , 1BvSvdvuvp'z   x& 6 > H N U ^ q z    x       v v!!v"!)!:!A!zS!Z!r!v|!!v!!v!! !x!!6! !!!%""z+"2"c9" >"x^" k"x"""""" "x" ""n"""R"#z+#2#9# >#x^# k#x###### #x# ##n####$z*$1$8$ @$x^$ g$y$ ~$x$ $$$ $$$$m$$$$%z!%(%13% 8%x_% l%% %x% %%n%n%%M%%%%& &.&A&z]&d&zo& w&x& &&m&m& &x' ' '''!'&'2'9'iJ'^'q'z''' 'x''' '''( ~, @1~6.= B~GNN S~\ a~mv {~ ~ ~   r~ P~ ~w25_:C J~PXa 8f~k}t y~~L `~ p~ ~&.5S< @A~FSNU^ c~hnu| ~ ~2 ~ ~k ~  @ r~!W( -~; D~JR[ `~eLjz @~ ~6BO  T~Zaj  o~t H ~ x ~  ~+   ~   ~"x+ 80~5 < A~F M  R~b pa  H~a   ~    ~x   ~  H ~   p ~ (  -~7C > C~M}V  [~i t p{~ ~ p~} `~   ~ ~} x~ ~, 7 p>~O HZ pa~o t~y ~W V~ ~ X~ ~ 8~  ~ o~ / 7~=W\b g~sz ~ X~ (~ p~~b 8~ i  ~ ' - ~7 < ~A rJ HO ~T [ ` ~e o t ~{  ~  H ~   ~  ~ C  ~ B ` ~ y  ~ l  ~   ~% / 4 ~9 @ xE ~J Q 8V ~] xb ~i t g   ~ x ~  ~  ` ~ x ~  ~ x ~  ~ x ~  ~& x+ ~: 8? ~F xK ~W \ ~c xh ~t y ~ x ~ 0 ~ x ~  ~ ] @  ~ 8  ~  0 ~  ` ~   ~% / 4 ~: B HI N ~S  \ a ~f x{ 0 ~ Q i  ~  ! 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